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Speed reading with the MCRC: a low noise, low power solution to quadruple X-ray CCD frame rates

Presentation #103.20 in the session Missions and Instruments.

Published onJul 01, 2023
Speed reading with the MCRC: a low noise, low power solution to quadruple X-ray CCD frame rates

The Advanced X-ray Imaging Satellite (AXIS) is a NASA probe class mission concept designed to deliver arcsecond resolution with an effective area ten times that of Chandra. The focal plane design for AXIS features MIT Lincoln Laboratory X-ray charge-coupled device (CCD) detectors coupled with a fast, low noise readout application specific integrated circuit (ASIC) under development at Stanford, denoted the Multi-Channel Readout Chip (MCRC). A successful MCRC prototype (MCRC-V1.0) has been manufactured in a 350 nm technology node featuring 8 channels, enabling parallel readout. Each channel is composed of two inputs. One will be paired with the proven source follower-based (SF) CCD architecture, where the main attributes include two selectable gain settings, an input referred noise of 1.63 e-RMS, an input dynamic range of ±160 mV, channel to channel crosstalk less than -75 dBc, a power consumption of roughly 35 mW/channel, and a full channel bandwidth of approximately 50 MHz. These performance parameters will enable readout speeds in excess of 5 Mpixel/s/channel, corresponding to more than 20 frames/s for the AXIS focal plane. The second input is an experimental drain-current readout (DR) topology, able to support Single electron Sensitive Read Out (SiSeRO) output stages, also currently in development at MIT-LL. The MCRC excels in speed and channel-to-channel isolation, while its input noise and bandwidth are comparable with commercial discrete offerings, though with much smaller power and area footprints. Here we present the latest measurement results for this prototype readout ASIC.

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